1. Field of the Invention
This invention relates to a robust method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of both a copper metal diffusion barrier layer and a copper seed layer, in a single and dual damascene process, to fabricate reliable metal interconnects and contact vias.
2. Description of Related Art
In the fabrication of semiconductor integrated circuits Prior Art methods of forming both a copper metal diffusion barrier layer and a copper seed layer, in dual damascene processing for interconnects and vias, widely use an ion metal plasma (IMP) to sputter deposit these layers prior to electrochemical deposition (ECD) of copper. The ion metal plasma (IMP) methods typically use either a plain deposition without AC/Rf bias or use a deposition with an AC/Rf bias xe2x80x9cONxe2x80x9d continuously, or combine the two types into a xe2x80x9ctwo stepxe2x80x9d process. The terms xe2x80x9cion deposition sputteredxe2x80x9d and xe2x80x9cion metal plasma (IMP) refer to sputter deposition, wherein a magnet array is placed behind the target (magnetron sputter deposition) and an inductively coupled Rf source is positioned between the target (cathode) and substrate. Some portion of the sputtered atoms arrive at the substrate in the form of charged ions. Also, the terms xe2x80x9creactive ion depositionxe2x80x9d or xe2x80x9creactive ion metal plasma (IMP) refer to ion-deposition sputtering wherein a reactive gas is supplied during sputtering, e.g., sputtering of Ta in N2 to form a TaN barrier layer. Related patents and relevant literature now follow as Prior Art.
U.S. Pat. No. 5,882,399 (Ngan et al.) describes an ion metal plasma (IMP) sputter process and tool set. The aluminum  less than 111 greater than  crystal orientation content of an aluminum interconnect layer or the copper  less than 111 greater than  crystal orientation content of a copper interconnect can be maintained at a consistently high value during the processing of an entire series of semiconductor substrates in a given process chamber. To provide the stable and consistent aluminum  less than 111 greater than  content, or the stable and consistent copper  less than 111 greater than  content, it is necessary that the barrier layer structure underlying the aluminum or the copper have a consistent crystal orientation throughout the processing of the entire series of substrates, as well. To ensure the consistent crystal orientation content of the barrier layer structure, it is necessary to form the first layer of the barrier layer structure to have a minimal thickness of at least about 150 xc3x85, to compensate for irregularities in the crystal orientation which may by present during the initial deposition of this layer. As an alternative to increasing the thickness of the first layer of the barrier layer structure, this first layer can be deposited at a low process chamber pressure, so that harmful irregularities in the crystal orientation are eliminated.
U.S. Pat. No. 5,654,233 (Yu) describes a barrier layer process that is interrupted with a partial etch back using reactive ion etch (RIE) to planarize an excessively thick barrier layer. It teaches a process for creating a planar topography and enhanced step coverage for the fabrication of contact/via holes in sub-half-micron diameter range with high height vs. dimension aspect ratio. This is accomplished by interrupting the deposition of the barrier layer in the contact/via lining with a programmed reactive ion etching process, which will protect the thin barrier lining in the bottom part of the contact hole, but will etch off and planarize the excessively thick barrier layer near the opening of the hole. The resulting barrier layers show a disrupt columnar film structure which provides better barrier during subsequent metal fill deposition process.
U.S. Pat. No. 5,897,368 (Cole, Jr. et al.) teaches a method for fabricating metallized vias with steep sidewalls. It includes applying a first seed layer extending over a horizontal surface and via sidewalls of a dielectric material and exposed underlying contact metallization; removing at least some of the first seed layer from the contact metallization and the horizontal surface while leaving a sufficient amount of the first seed layer on the sidewalls as a catalyst for subsequent application of a third seed layer; sputtering a second seed layer over the contact metallization and the horizontal surface; using an electroless solution to react with the first seed layer and apply the third seed layer over the sidewalls; and electroplating an electroplated layer over the second and third seed layers.
U.S. Pat. No. 5,821,160 (Jain) describes a process for forming a semiconductor device in which an insulating layer is nitrided and then covered by a thin adhesion layer before depositing a composite copper layer. This process does not require a separate diffusion barrier as a portion of the insulating layer has been converted to form a diffusion barrier film. Additionally, the adhesion layer is formed such that it can react with the interconnect material resulting in strong adhesion between the composite copper layer and the diffusion barrier film, as well as, allow a more continuous interconnect and via structure.
U.S. Pat. No. 5,316,974 (Crank) describes a process for forming a copper seed layer. A metallized structure is formed from a copper seed layer and a copper structure. Semiconductor devices to be connected are covered by a conductive barrier layer. An oxide layer is then deposited over the barrier layer and patterned using standard photolithographic techniques and an anisotropic plasma etch. Vertical side walls are formed by the etch and an HF deglaze. A seed layer is then sputtered onto a photoresist layer and the exposed barrier layer. After stripping the photoresist and the seed layer thereon, the copper structure is electroplated over the remaining seed layer. The structure thus formed has approximately vertical sidewalls for improved contact with subsequent layers.
It is a general object of the present invention to provide a new and improved robust method of forming both a copper metal diffusion barrier layer and a copper seed layer, in a single and dual damascene process, to fabricate reliable metal interconnects and contact vias.
For completeness provided by the present invention, is a semiconductor substrate with a an insulting layer thereon. A copper metal interconnect typically is patterned within an insulating layer. In addition, a layer of interlevel dielectric (ILD) is deposited and patterned into a trench structure or xe2x80x9cgapxe2x80x9d opening. Provided can be both a single and dual damascene structure.
A more specific object of the present invention is to provide an improved method of forming an integrated circuit in which the metal diffusion barrier layer and copper seed layer are both deposited by an improved method of deposition which differs significantly from conventional methods. The present invention makes use of the following deposition techniques for the barrier layer and copper seed layer: xe2x80x9cion deposition sputteringxe2x80x9d and xe2x80x9cion metal plasmaxe2x80x9d (IMP) sputtering, wherein a magnet array is placed behind the target (magnetron sputter deposition) and an inductively coupled Rf source is positioned between the target (cathode) and substrate. Some portions of the sputtered atoms arrive at the substrate in the form of charged ions. In addition, the present invention makes use of xe2x80x9creactive ion depositionxe2x80x9d or xe2x80x9creactive ion metal plasma (IMP), wherein a reactive gas is supplied during sputtering in the deposition of a barrier layer of Ta in N2.
The main embodiments of the present invention, the above and other objectives are realized by using a multi-step method of fabricating metal barrier layer and copper seed layer. The present invention teaches a method of combining ion metal plasma (IMP) deposition techniques, i.e., with and without AC/Rf bias, in a series of steps or cycles (of at least four or more cycles depending on device geometry), of AC/Rf bias xe2x80x9cONxe2x80x9d, AC/Rf bias xe2x80x9cOFFxe2x80x9d, to form both the copper metal diffusion barrier (reactive IMP) and then subsequently, the copper seed layer. The current invention applies to lining both a single and dual damascene structure to form a copper metal barrier layer, TaN, and copper seed layer for interconnects and vias prior to electrochemical deposition (ECD) of copper.
In the first embodiment of the present invention, the uniform defect-free copper metal barrier layer is formed by reactive ion metal plasma (IMP) deposition sputtering, e.g., Ta from a target (cathode) and reacting Ta with a nitrogen gas ambient to yield TaN. The reactive ion metal plasma (IMP) deposition is performed with and without AC/Rf bias, in a series of steps or cycles (of at least four or more cycles depending on device geometry), of AC/Rf bias xe2x80x9cONxe2x80x9d, AC/Rf bias xe2x80x9cOFFxe2x80x9d, to form the copper metal diffusion barrier (reactive IMP). The process can be extended to Ta/TaN/TaN barrier layers for better adhesion.
In the second embodiment of the present invention, similar to the multi-step deposition of the barrier layer, a uniform defect-free copper seed layer is ion metal plasma (IMP) deposited (without reactive sputtering), i.e., with and without AC/Rf bias, in a series of steps or cycles (of at least four or more cycles depending on device geometry), of AC/Rf bias xe2x80x9cONxe2x80x9d, AC/Rf bias xe2x80x9cOFFxe2x80x9d, to form both the copper seed layer.
Another object of the present invention is to provide an improved method of forming copper interconnect and via contacts. Therefore, for completeness, is the next processing step in building of a single or dual damascene structure, the deposition of copper upon the seed layer, by electrochemical copper deposition (ECD). The kinetics of the electroless copper deposition process are based on a uniform, defect-free seed layer. It is the aforementioned defects in the seed layer and in ECD fill of the single and dual damascene structures, that the present invention addresses and provides solutions to these process problems. The final processing step in building of the single and dual damascene structure is the chemical mechanical polishing (CMP) back of the excess electroless deposited copper metal, excess seed layer and excess barrier layer. The copper is chem-mech polished back without dishing. Device applications include MOSFET and CMOS devices.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.